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| M68Z512 4 Mbit (512Kb x8) Low Power SRAM with Output Enable s ULTRA LOW DATA RETENTION CURRENT - 100nA (typical) - 10A (max) s s s s s s s OPERATION VOLTAGE: 5V 10% 512 Kbit x8 SRAM with OUTPUT ENABLE EQUAL CYCLE and ACCESS TIMES: 70ns LOW VCC DATA RETENTION: 2V TRI-STATE COMMON I/O CMOS for OPTIMUM SPEED/POWER AUTOMATIC POWER-DOWN WHEN DESELECTED INTENDED FOR USE WITH ST ZEROPOWER(R) AND TIMEKEEPER (R) CONTROLLERS 32 1 TSOP II 32 (NC) 10 x 20mm s Figure 1. Logic Diagram DESCRIPTION The M68Z512 is a 4 Mbit (4,194,304 bit) CMOS SRAM, organized as 524,288 words by 8 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 5V 10% supply, and all inputs and outputs are TTL compatible. This device has an automatic power-down feature, reducing the power consumption by over 99% when deselected. The M68Z512 is available in a 32 lead TSOP II (10 x 20mm) package. Table 1. Signal Names A0-A18 DQ0-DQ7 E G W VCC VSS Address Inputs VCC 19 A0-A18 8 DQ0-DQ7 W E G M68Z512 Data Input/Output Chip Enable Output Enable Write Enable Supply Voltage Ground VSS AI03030 March 2000 1/12 M68Z512 Table 2. Absolute Maximum Ratings (1) Symbol TA TSTG VIO (2) VCC IO (3) PD Parameter Ambient Operating Temperature Storage Temperature Input or Output Voltage Supply Voltage Output Current Power Dissipation Value 0 to 70 -65 to 150 -0.3 to VCC + 0.3 -0.3 to 7.0 20 1 Unit C C V V mA W Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Up to a maximum operating VCC of 5.5V only. 3. One output at a time, not to exceed 1 second duration. Figure 2. TSOP Connections A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 32 8 9 M68Z512 25 24 16 17 AI03031 VCC A15 A18 W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 READ MODE The M68Z512 is in the Read mode whenever Write Enable (W) is High with Output Enable (G) Low, and Chip Enable (E) is asserted. This provides access to data from eight of the 4,194,304 locations in the static memory array, specified by the 19 address inputs. Valid data will be available at the eight output pins within tAVQV after the last stable address, providing G is Low and E is Low. If Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parameter (t ELQV or tGLQV) rather than the address. Data out may be indeterminate at tELQX and tGLQX, but data lines will always be valid at tAVQV. WRITE MODE The M68Z512 is in the Write mode whenever the W and E pins are Low. Either the Chip Enable input (E) or the Write Enable input (W) must be deasserted during Address transitions for subsequent write cycles. Write begins with the concurrence of Chip Enable being active with W low. Therefore, address setup time is referenced to Write Enable and Chip Enable as tAVWL and tAVEH respectively, and is determined by the latter occurring edge. The Write cycle can be terminated by the earlier rising edge of E, or W. if the Output is enabled (E = Low and G = Low), then W will return the outputs to high impedance within t WLQZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. Data input must be valid for tDVWH before the rising edge of Write Enable, or for t DVEH before the rising edge of E, whichever occurs first, and remain valid for tWHDX or tEHDX. 2/12 M68Z512 Table 3. Operating Modes Operation Read Read Write Deselect Note: 1. X = VIH or VIL. E VIL VIL VIL VIH W VIH VIH VIL X G VIH VIL X X DQ0-DQ7 Hi-Z Data Output Data Input Hi-Z Power Active Active Active Standby Table 4. AC Measurement Conditions Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 5ns 0 to 3V 1.5V Figure 3. AC Testing Load Circuit 5.0V Note: Output Hi-Z is defined as the point where data is no longer driven. 1838 DEVICE UNDER TEST 994 OPERATIONAL MODE The M68Z512 has a Chip Enable power down feature which invokes an automatic standby mode whenever Chip Enable is de-asserted (E = High). An Output Enable (G) signal provides a high speed tri-state control, allowing fast read/write cycles to be achieved with the common I/O data bus. Operational modes are determined by device control inputs W and E as summarized in the Operating Modes table. OUT CL = 100pF or 5pF CL includes JIG capacitance AI03032 Table 5. Capacitance (1) (TA = 25C, f = 1 MHz) Symbol CIN COUT (2) Parameter Input Capacitance on all pins (except DQ) Output Capacitance Test Condition TA = 25C, f = 1MHz, VCC = 5V TA = 25C, f = 1MHz, VCC = 5V Min Max 6 8 Unit pF pF Note: 1. Sampled only, not 100% tested. 2. Outputs deselected. 3/12 M68Z512 Figure 4. Block Diagram A (10) A CHIP ENABLE. DQ (8) DQ INPUT DATA CTRL I/O CIRCUITS COLUMN DECODER ROW DECODER MEMORY ARRAY VCC VSS CHIP ENABLE. (9) A E W A G AI03033 Table 6. DC Characteristics (TA = 0 to 70C; VCC = 5V 10%) Symbol ILI ILO ICC1 ICC2 (1) (2) Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Test Condition 0V VIN VCC 0V VOUT VCC VCC = 5.5V, (-55) VCC = 5.5V, E = VIH VCC = 5.5V, E VCC - 0.3V, f=0 Min Typ Max 1 1 90 15 Unit A A mA mA A V V V V ICC3 (3) VIL VIH VOL VOH 1.6 -0.3 2.2 20 0.8 VCC + 0.3 0.4 IOL = 2.1mA IOH = -1mA 2.4 Note: 1. Average AC current, Outputs open, cycling at tAVAV minimum. 2. All other Inputs at V IL 0.8V or VIH 2.2V. 3. All other Inputs at V IL 0.3V or VIH VCC -0.3V. 4/12 M68Z512 Table 7. Read and Standby Modes AC Characteristics (TA = 0 to 70C; VCC = 5V 10%) M68Z512 Symbol Parameter Min tAVAV tAVQV (1) tELQV (1) tGLQV (1) tELQX (3) tGLQX (3) tEHQZ (2,3) tGHQZ (2,3) tAXQX (1) tPU tPD Read Cycle Time Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable Low to Output Transition Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition Chip Enable Low to Power Up Chip Enable High to Power Down 10 0 70 10 5 25 25 70 70 70 35 -70 Max ns ns ns ns ns ns ns ns ns ns ns Unit Note: 1. CL = 100pF. 2. CL = 5pF. 3. At any given temperature and voltage condition, tEHQZ is less than t ELQX and tGHQZ is less than t GLQX for any given device. Figure 5. Address Controlled, Read Mode AC Waveforms tAVAV A0-A18 tAVQV VALID tAXQX DQ0-DQ7 DATA VALID AI03034 Note: E = Low, G = Low, W = High. 5/12 M68Z512 Figure 6. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms. tAVAV A0-A18 tAVQV tELQV E tELQX tGLQV G tGLQX DQ0-DQ7 VALID AI03035 VALID tAXQX tEHQZ tGHQZ Note: Write Enable (W) = High. Figure 7. Standby Mode AC Waveforms E ICC1 ICC2 tPU 50% tPD AI03036 6/12 M68Z512 Table 8. Write Mode AC Characteristics (TA = 0 to 70C; VCC = 5V 10%) M68Z512 Symbol Parameter Min tAVAV tAVWL tAVWH tAVEH tWLWH tWHAX tWHDX tWHQX (2) tWLQZ (1,2) tAVEL tELEH tEHAX tDVWH tDVEH Write Cycle Time Address Valid to Write Enable Low Address Valid to Write Enable High Address Valid to Chip Enable High Write Enable Pulse Width Write Enable High to Address Transition Write Enable High to Input Transition Write Enable High to Output Transition Write Enable Low to Output Hi-Z Address Valid to Chip Enable Low Chip Enable Low to Chip Enable High Chip Enable High to Address Transition Input Valid to Write Enable High Input Valid to Chip Enable High 0 45 0 25 25 70 0 60 60 55 0 0 5 25 -70 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Note: 1. CL = 5pF. 2. At any given temperature and voltage condition, tWLQZ is less than tWHQX for any given device. 7/12 M68Z512 Figure 8. Write Enable Controlled, Write AC Waveforms tAVAV A0-A18 VALID tAVWH tAVEL E tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH AI03037 tWHAX tWHQX Note: Output Enable (G) = Low. Figure 9. Chip Enable Controlled, Write AC Waveforms (1,2) tAVAV A0-A18 VALID tAVEH tAVEL E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH AI03038 tELEH tEHAX Note: 1. Output Enable (G) = High. 2. If E goes High with W high, the output remains in a high-impedance state. 8/12 M68Z512 Table 9. Low V CC Data Retention Characteristics (TA = 0 to 70C) Symbol ICCDR VDR tCDR tER (2) (1) Parameter Supply Current (Data Retention) Supply Voltage (Data Retention) Chip Disable to Power Down Operation Recovery Time Test Condition VCC = 3V, E VCC - 0.3V E VCC - 0.3V, f = 0 E VCC - 0.3V, f = 0 Min Typ 0.1 Max 10 Unit A V ns ns 2 0 tAVAV Note: 1. Typical condition: T A = 25C. 2. See Figure 10 for measurement points. Guaranteed but not tested. tAVAV is Read cycle time. Figure 10. Low VCC Data Retention AC Waveforms DATA RETENTION MODE 5V VCC 3V VDR > 2.0V tCDR E VDR - 0.3V E 2.2V tER AI03039 9/12 M68Z512 Table 10. Ordering Information Scheme Example: Device Type M68Z Device Function 512 = 4 Mbit (512Kb x8) Operating Voltage blank = 4.5V to 5.5V Speed -70 = 70 ns Package NC = TSOP II 32 (10 x 20mm) Temperature Range 1 = 0 to 70 C Shipping Method T = Tape & Reel Packing M68Z512 -70 NC 1 T For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. Table 11. Revision History Date May 1999 03/14/00 First Issue TSOP32 II Package Dimension Changed (Table 12) From Preliminary Data to Data Sheet Revision Details 10/12 M68Z512 Table 12. TSOP II 32 - 32 lead Plastic Thin Small Outline II, 10 x 20 mm, Package Mechanical Data mm Symbol Typ A A1 A2 b C CP D e E E1 L N 1.27 20.82 - 11.56 10.03 0.40 0 32 0.05 0.95 0.30 0.12 Min Max 1.20 0.15 1.05 0.52 0.21 0.10 21.08 - 11.96 10.29 0.60 5 0.050 0.820 - 0.455 0.395 0.016 0 32 0.002 0.037 0.012 0.005 Typ Min Max 0.047 0.006 0.041 0.020 0.008 0.004 0.830 - 0.471 0.405 0.024 5 inch Figure 11. TSOP II 32 - 32 lead Plastic Thin Small Outline II, 10 x 20 mm, Package Outline D 16 1 E1 E 17 32 b e A A2 C A1 CP L TSOP-d Drawing is not to scale. 11/12 M68Z512 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics (R) 2000 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 12/12 |
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